The invention relates generally to semiconductor device fabrication and, in particular, to methods and structures for enhancing the homogeneity in a ratio of perimeter to surface area among heterogeneous features in different regions on a substrate.
Integrated circuits consist of devices, such as transistors and diodes, and other types of circuit elements, such as resistors and capacitors, linked together by conductive connections to form one or more functional electrical circuits. The devices and circuit elements are manufactured using a wafer that is subjected to a series of fabrication steps to form a pattern of identical integrated circuits. Following manufacture, the integrated circuits are separated from each other by a rectangular pattern of scribe lines or saw streets that serve as boundaries between the discrete chips or dice on the wafer. After singulation into discrete chips, each die is bonded to a substrate to define a packaged device.
The fabrication steps used to manufacture an integrated circuit generally involve the deposition and patterning of a series of layers of insulating and conductive materials. In certain cases, the inherent geometric properties of conformal materials may be used, rather than lithographic steps, for defining feature edges adjacent to other topological features. Layers deposited on planar surfaces may exhibit a high degree of thickness uniformity as a fraction of their overall thickness. However, the deposited thickness of a conformal layer on surfaces with features that supply a three-dimensional topography may vary in relationship to the local perimeter density of the underlying features.
The perimeter density is linked to the topography of the features by the number of feature edges. The resulting variations in layer thickness caused by the dependence on perimeter density may significantly impact device performance. In some instances, the variation in device performance may be as high as ten percent. For example, variations in the local pattern density may affect spacer thicknesses on gate electrodes of field effect transistors formed by complementary metal-oxide-semiconductor (CMOS) processes in different regions of an integrated circuit. In regions of high perimeter density for the gate electrodes, the thickness of the dielectric layer etched to define the spacers may be thinner than in regions of low perimeter density. Hence, the spacer thickness is reduced in high perimeter density regions, which causes the field effect transistors to be faster in these regions or to exhibit increased leakage in comparison with regions of low perimeter density for the gate electrodes. Differences in perimeter density may cause the spacer thickness to vary on different sidewalls of individual gate electrodes within a region. These resulting variations in device speed may cause introduce circuit timing problems.
Traditional rules for pattern density homogeneity, which are applied as constraints during circuit design, fail to address layer thickness variations arising from inhomogeneities in perimeter density. Designers must combine maximum linewidth and wide-line/wide-space rules with maximum local density rules. However, certain geometrical configurations of layout elements can obey all design rules and yet still be difficult to reliably manufacture. For example, the layout of gate electrodes may satisfy all design rules but yet experience significant variations in conformal film thickness because of the aforementioned perimeter density variations.
Improved methods and structures are needed that improve the deposition homogeneity of conformal layers on surfaces characterized by a surface topography with local variations in perimeter density.